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IDT74ALVC16835 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
FEATURES: DESCRIPTION:
IDT74ALVC16835
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V 0.3V, Normal Range * VCC = 2.7V to 3.6V, Extended Range * VCC = 2.5V 0.2V * CMOS power levels (0.4 W typ. static) * Rail-to-Rail output swing for increased noise margin * Available in SSOP, TSSOP, and TVSOP packages
This 18-bit universal bus driver is built using advanced dual metal CMOS technology. Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode when the latchenable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch flip-flop on the low-to-high transition of CLK. When OE is high, the outputs are in the high-impedance state. The ALVC16835 has been designed with a 24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
DRIVE FEATURES:
* High Output Drivers: 24mA * Suitable for heavy loads
APPLICATIONS:
* SDRAM Modules * PC Motherboards * Workstations
FUNCTIONAL BLOCK DIAGRAM
OE
27
CLK
30
LE
28
A1
54
1D
3
C1 CLK
Y1
TO 17 OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
(c) 1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4478/1
IDT74ALVC16835 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Max VTERM(2) Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Continuous Clamp Current, VI < 0 or VI > VCC Continuous Clamp Current, VO < 0 Continuous Current through each VCC or GND -0.5 to +4.6 -0.5 to VCC+0.5 -65 to +150 -50 to +50 50 -50 100 VTERM(3) TSTG IOUT IIK IOK ICC ISS
Unit V V C mA mA mA mA
NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND NC A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLK GND
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT COUT Parameter(1) Input Capacitance Output Capacitance I/O Port Capacitance Conditions VIN = 0V VOUT = 0V VIN = 0V Typ. 5 7 7 Max. 7 9 9 Unit pF pF pF
NOTE: 1. As applicable to the device type.
FUNCTION TABLE(1)
Inputs OE H L L L L L LE X H H L L L L CLK X X X H L Ax X L H L H X X Outputs Yx Z L H L H Y0 Y0
(2) (3)
SSOP/ TSSOP/ TVSOP TOP VIEW
PIN DESCRIPTION
Pin Names OE CLK LE Ax Yx NC Description 3-State Output Enable Inputs (Active LOW) Register Input Clock Latch Enable (Transparent LOW) Data Inputs 3-State Outputs No Internal Connection 2
L
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established, provided that CLK is HIGH before LE went HIGH. 3. Output level before the indicated steady-state input conditions were established.
IDT74ALVC16835 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = -40C to +85C
Symbol VIH VIL IIH IIL IOZH IOZL VIK VH ICCL ICCH ICCZ ICC Parameter Input HIGH Voltage Level Input LOW Voltage Level Input HIGH Current Input LOW Current High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current VCC = 2.3V, IIN = -18mA VCC = 3.3V VCC = 3.6V VIN = GND or VCC One input at VCC - 0.6V, other inputs at VCC or GND VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 2.3V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VI = VCC VI = GND VO = VCC VO = GND Test Conditions Min. 1.7 2 -- -- -- -- -- -- -- -- -- Typ.(1) -- -- -- -- -- -- -- -- -0.7 100 0.1 Max. -- -- 0.7 0.8 5 5 10 10 -1.2 -- 40 V mV A A A A V Unit V
Quiescent Power Supply Current Variation
--
--
750
A
NOTE: 1. Typical values are at VCC = 3.3V, +25C ambient.
OUTPUT DRIVE CHARACTERISTICS
Symbol VOH Parameter Output HIGH Voltage VCC = 2.3V VCC = 2.3V VCC = 2.7V VCC = 3V VCC = 3V VOL Output LOW Voltage VCC = 2.3V to 3.6V VCC = 2.3V VCC = 2.7V VCC = 3V IOH = - 24mA IOL = 0.1mA IOL = 6mA IOL = 12mA IOL = 12mA IOL = 24mA Test Conditions(1) VCC = 2.3V to 3.6V IOH = - 0.1mA IOH = - 6mA IOH = - 12mA Min. VCC - 0.2 2 1.7 2.2 2.4 2 -- -- -- -- -- Max. -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 V Unit V
NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = - 40C to + 85C.
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IDT74ALVC16835 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, TA = 25C
VCC = 2.5V 0.2V Symbol CPD CPD Parameter Power Dissipation Capacitance Outputs enabled Power Dissipation Capacitance Outputs disabled Test Conditions CL = 0pF, f = 10Mhz Typical 26 12 VCC = 3.3V 0.3V Typical 31 15 Unit pF
SWITCHING CHARACTERISTICS(1)
VCC = 2.5V 0.2V Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tW tW tSU tSU tSU tH tH tSK(O) Propagation Delay Ax to Yx Propagation Delay LE to Yx Propagation Delay CLK to Yx Output Enable Time OE to Yx Output Disable Time OE to Yx Pulse Duration, LE LOW Pulse Duration, CLK HIGH or LOW Set-up Time, data before CLK Set-up Time, data before LE, CLK HIGH Set-up Time, data before LE, CLK LOW Hold Time, data after CLK Hold Time, data after LE, CLK HIGH or LOW Output Skew(2) 3.3 3.3 2.2 1.9 1.3 0.6 1.4 -- -- -- -- -- -- -- -- -- 3.3 3.3 2.1 1.6 1.1 0.6 1.7 -- -- -- -- -- -- -- -- -- 3.3 3.3 1.7 1.5 1 0.7 1.4 -- -- -- -- -- -- -- -- 500 ns ns ns ns ns ns ns ps 1 4.5 -- 4.3 1.3 3.9 ns 1.4 5.5 -- 5.6 1.1 4.6 ns 1.4 5.5 -- 5.2 1.4 4.5 ns 1.3 5 -- 4.9 1.3 4.2 ns Parameter Min. 150 1 Max. -- 4.2 VCC = 2.7V Min. 150 -- Max. -- 4.2 VCC = 3.3V 0.3V Min. 150 1 Max. -- 3.6 Unit MHz ns
NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = - 40C to + 85C. 2. Skew between any two outputs of the same package and switching in the same direction.
SWITCHING CHARACTERISTICS FROM 0C TO 65C, CL = 50pF
VCC = 3.3V 0.15V Symbol tPLH tPHL Parameter Propagation Delay CLK to xYx Min. 1.7 Max. 4.5 Unit ns
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IDT74ALVC16835 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
VIH VT 0V VOH VT VOL VIH VT 0V
ALV C Link
TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS
Symbol VLOAD VIH VT VLZ VHZ CL VCC(1)= 3.3V0.3V VCC(1)= 2.7V 6 2.7 1.5 300 300 50
VCC 500 Pulse Generator
(1, 2)
SAME PHASE INPU T TRAN SITION
VCC(2)= 2.5V0.2V 2 x Vcc Vcc Vcc / 2 150 150 30
Unit V V V mV mV pF
VLOAD Open GND
tPLH OU TPUT tPLH OPPOSITE PHASE INPU T TRAN SITION
tPHL
6 2.7 1.5 300 300 50
tPHL
Propagation Delay
ENABLE CON TROL IN PUT tPZL
DISABLE
VIN D .U .T.
VOUT
VIH VT 0V VLOAD/2 VOL + VLZ VOL VOH VOH - VHZ 0V
ALV C Link
tPLZ VLOAD/2 VT tPHZ VT 0V
RT
500 CL
ALVC Link
Test Circuit for All Outputs
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2.5ns; tR 2.5ns. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tF 2ns; tR 2ns.
OUTPU T SW ITCH NOR MALLY CLO SED LOW tPZH OU TPUT SW ITCH NORMALLY O PE N H IGH
NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V
ALVC Link
Enable and Disable Times
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch VLOAD GND Open
VIH INPU T VT 0V VOH OUTPUT 1 VT VOL VOH OUTPUT 2 tPLH2 tPHL2
ALVC Link
DATA INPUT TIMING INPU T ASYNC HRON OU S CON TROL SYNC HRON OU S CON TROL
tSU
tH
tREM
tSU
tH
Set-up, Hold, and Release Times
tPLH1
tPHL1
LOW -H IGH -LOW PULSE tW HIGH-LOW -HIGH PULSE
VT
tSK (x)
tSK (x)
VT
ALVC Link
VT VOL
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew - tSK(X)
NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
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IDT74ALVC16835 3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT ALVC X XX Bus-Hold Temp. Range XXX Family XXX XX Device Type Package
PV PA PF 835 16
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package 18-Bit Universal Bus Driver with 3-State Outputs Double-Density, 24mA
Blank No Bus-Hold 74 -40C to +85C
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